1. Field of the Invention
The invention relates to integrated circuit devices and more particularly to reducing timing variations due to the fabrication and operation of such devices.
2. Description of Related Art
A major goal of metal oxide semiconductor field effect transistor (MOSFET) fabrication is to increase the density and consequently speed of the integrated circuits in which such devices are utilized. To gain performance increases, the saturation drain current (I.sub.Dsat) is increased typically by a decrease in the channel length and a decrease in the gate oxide thickness.
Integrated circuit chips or dies may have millions of devices. To fabricate such chips usually begins by computer-aided design (CAD) systems. CAD systems assemble the individual components into circuit layout patterns and draw a composite picture of the circuit surface showing all of the sub-layer patterns. This information is typically transferred to a reticle that is a hard copy of the individual drawing that may be used to pattern a wafer surface.
Patterning the wafer surface involves various steps of deposition, diffusion, etching, implantation, lithography, etc. There are probabilistic components in each of the physical formation steps of a die. For instance, though the CAD design may call for a particular gate length L, the effective gate length (L.sub.eff) which may be deposited and patterned by deposition, diffusion, and etching steps to coincide slightly differently than the desired L. Thus, a fabrication process ideally targeted for typical process parameters will have inherent variations that either speed up or slow down the device because of the variations in the fabrication of the devices. The variations can be classified as either systematic or random. In the ordinary case, these various physical process steps in the formation of the integrated circuit die create a systematic and random "skew" in the sense that circuit speed of the die is slower because, once fabricated, individual threshold voltages of the device were slightly higher than desired or the effective gate length of the individual devices of the integrated circuit was slightly larger than desired.
In addition to the systematic and random variations in individual device level performance caused by the fabrication of such devices of an integrated circuit, there are further systematic variations presented because of the die environment. In other words, the environment around a particular device has a significant effect on the performance of that device. For example, tightly spaced gates may interact with one another or the middle gate of an array of three adjacent gates may act differently, although drawn and fabricated identically to its adjacent gates, based on the environmental effects those adjacent gates have on that device.
Further, trends in integrated circuit fabrication call for increases in die sizes to accommodate faster processing speeds. As such, devices on a larger die will encompass a larger area. Integral devices on a smaller die might be closer together than the same devices would be on a larger die. The change in environmental effects due to die size on smaller dies is less than the change in environmental effects on a larger die. Thus, increasing die size will also tend to increase the systematic and random variations inherent in a device and will have greater effects on the overall timing budget of a die.
Thus, it is known to those studied in the art that there are systematic and random errors in layout. Techniques for compensating for the systematic errors have been devised. These techniques include layout compensation, compensation of dimension, and redrawing certain legs of the circuit either at the transistor or metal layout level. More specifically, these methods include analog current matching, centroid or x-layouts, and interpolation compensation schemes. These efforts have all been targeted at reducing systematic skews in devices that reduce timing margins and switching frequency.
As dies get larger, as critical dimensions decrease to the deep submicron level, as speeds increase, the systematic and random variations become a more significant part of the timing budget. To date, the majority of efforts to address the variations in chip fabrication have been directed at the systematic variations, to the exclusion of the random process variations.